1. Field of the Invention
This invention relates to a synchronous DRAM capable of continuously reading/writing data stored in a plurality of memory cells by a single read/write operation.
2. Description of the Related Art
A synchronous DRAM (Dynamic Random Access Memory) has a feature that it can continuously read and write at a high speed data having a desired length. Because of this feature, the synchronous DRAM has been used mainly as a storage device for storing data that are continuously read/written, such as image data. Recently, the capacity of the synchronous DRAM has been increased, too, and devices having a capacity greater than the capacity required for an image memory have been developed.
A memory system utilizing the conventional synchronous DRAM will be explained with reference to FIG. 1. Burst length and CAS latency are set as data for defining an operation mode of a synchronous DRAM 401 to a mode register set 411 provided to the synchronous DRAM 401. This setting is executed at the time of making of power. The burst length is used for controlling an address generation process by an input control circuit 412. CAS latency is used for executing delay control in a data output processing by an output control circuit 413.
When a controller 402 outputs a control signal designating a read operation with an address A0 to a bus, the input control circuit 412 outputs a control signal designating a data read operation to a memory array 415. At the same time, addresses of a length corresponding to the burst length are generated with the address A0 as the leading address, and are serially inputted to an address decoder 414. The content of corresponding memory cells is serially read out from the memory array 415 in accordance with the decoding result obtained by the address decoder 414 and are outputted to the bus through the output control circuit 413.
On the other hand, when the address AN is inputted with the control signal designating the write operation, the input control circuit 412 outputs the control signal designating the data write operation to the memory array 415. Continuous addresses of a length corresponding to the burst length are generated with the address AN as the leading address, and are serially inputted to the address decoder 414. The data inputted to the input control circuit 412 through the data bus are serially written to the memory cells designated by the decoding result obtained by the address decoder 414.
Setting of the operation mode to the conventional synchronous DRAM 401 is conducted in the following procedure.
1. First, the controller 402 generates a control signal for bringing the synchronous DRAM 401 into an idle mode, and inputs this signal to the synchronous DRAM.
2. The controller 402 then inputs a predetermined address signal to the synchronous DRAM 401 and sets the mode register set 411.
3. After the operation mode to the mode register set is thus completed, the controller 402 inputs a control signal representing an active command to the synchronous DRAM 401. In consequence, the synchronous DRAM 401 shifts to a readable active condition.
In the application of the conventional synchronous DRAM, the read and write operations are executed ordinarily in accordance with the operation mode set in the way described above at the time of turning-on power.
Because synchronous DRAMs having a large capacity have now been developed, the application of such synchronous DRAMs to the application of a shared memory that is accessed in common by a plurality of controllers has been expected. For example, utilization of one synchronous DRAM not only as the image memory but also as program storage is expected.
However, the conventional synchronous DRAM is fabricated on the assumption that the memory is accessed as a whole by a single controller. Therefore, setting of the burst length and CAS latency has been made for the synchronous DRAM as a whole.
When image data corresponding to a plurality of cells are continuously read out from a part of the memory array of the synchronous DRAM, therefore, the burst length and CAS latency suitable for such image data must be set beforehand to the mode register set. When an access is made to the program data, the burst length and CAS latency suitable for the program data must be set once again to the mode register set, too. To change setting of the mode register set, the controller must execute the operations of the three stages of 1 to 3 described above.
As described above, when a plurality of controllers gains access to the synchronous DRAM in different operation modes, setting of the operation mode must be changed frequently, and performance of the overall processing drops remarkably due to this setting processing.
On the other hand, if the operation mode for the read/write operation directed to a single memory cell is set in the same way as in the case of the ordinary memory, a plurality of controllers can gain access in common. In this case, however, the operation mode for executing the read/write operation directed to the single memory cell is applied to the image data for which the operation mode for continuously reading long data is effective, and high-speed performance expected of the utilization of the synchronous DRAM cannot be exploited.